// Created by ihdl
module DIVN_CNTR_DW01_inc_0 (
	A, 
	SUM);
   input [6:0] A;
   output [6:0] SUM;

   // Internal wires
   wire carry_6_;
   wire carry_5_;
   wire carry_4_;
   wire carry_3_;
   wire carry_2_;

   HAX1 U1_1_5 (.YS(SUM[5]), 
	.YC(carry_6_), 
	.B(carry_5_), 
	.A(A[5]));
   HAX1 U1_1_4 (.YS(SUM[4]), 
	.YC(carry_5_), 
	.B(carry_4_), 
	.A(A[4]));
   HAX1 U1_1_3 (.YS(SUM[3]), 
	.YC(carry_4_), 
	.B(carry_3_), 
	.A(A[3]));
   HAX1 U1_1_2 (.YS(SUM[2]), 
	.YC(carry_3_), 
	.B(carry_2_), 
	.A(A[2]));
   HAX1 U1_1_1 (.YS(SUM[1]), 
	.YC(carry_2_), 
	.B(A[0]), 
	.A(A[1]));
   XOR2X1 U1 (.Y(SUM[6]), 
	.B(A[6]), 
	.A(carry_6_));
   INVX1 U2 (.Y(SUM[0]), 
	.A(A[0]));
endmodule
